The present invention relates in general to hardware design and manufacturing, and more specifically, to methods, systems and computer program products for verification of an integrated circuit design.
In the field of electronic hardware design and manufacturing (e.g., computing or processing circuit design within an integrated circuit (IC) or semiconductor chip), verification of the often relatively complex hardware design prior to manufacturing is paramount. Unchecked or unfound subtle design flaws, errors or “bugs” pose various types of risk. Thus, numerous and various techniques exist for hardware design verification, including the related task of security verification. These techniques oftentimes comprise a significant portion of the total cost of the overall hardware design.